A simulation study on pseudomorphic high electron mobility transistors (pHEMT) fabricated using the GaInP/InGaAs material system

Abstract

The DC and RF characteristics of the 0.35 μm gate length Ga 0.52In 0.48P/In 0.2Ga 0.8As/Ga 0.52In 0.48P double-heterojunction pseudomorphic high electron mobility transistor (DH-pHEMT) and 0.25 μm gate length single-heterojunction Ga 0.52In 0.48P/In 0.2Ga 0.8As/GaAs (SH-pHEMT) were simulated using a two-dimensional device simulator, MEDICI [12], with the incorporation of the Ga x In 1− x As y P 1− y quaternary well formed between GaInP and InGaAs layers. By including the interfacial layers between the GaInP-on-InGaAs layers (and vice versa), the simulator is able to model and give an insight into the transconductance behavior of these devices, namely the second transconductance peak of lower magnitude at negative gate biases observed for double heterojunctions and the high transconductance maintained at positive gate biases for the single-heterojunction devices. The simulation program was also used to predict the performance of a pHEMT, which uses a strained barrier (Ga 0.60In 0.40P) to suppress the undesired effects of the interfacial quaternary layers formed at the heterojunctions. Hall measurements revealed that higher electron mobility in the channel was obtained in this structure and simulations showed that high transconductance and good device behavior is obtainable despite lower electron concentrations. The fabricated device exhibited a peak transconductance, G m, of 470 mS/mm, maximum drain current, I DS max , of 550 mA/mm and current gain cut-off frequency, f T, of 50 GHz.