A simulated annealing based method supporting dual supply voltages in standard cell placement

Abstract

Allowing different supply voltages for different gates in the same circuit is one of the approaches that achieves power reduction. Previous researches focused on determining the voltage level for each gate and ascertaining the power saving capability of the approach via logic-level power estimation. In this paper, we present a layout technique that feasibilizes the approach in a cell-based design environment. A new block layout style is proposed to support the voltage scaling with conventional standard cell libraries. The block layout can be automatically generated via a simulated annealing based placement algorithm. Experimental results show that proposed techniques produce very promising results.