Abstract

This paper presents a simple explicit compact model for the drain current of long channel symmetrical junctionless Double Gate MOSFETs. Our approach leads to very simple equations compared to other models, while retaining high accuracy and physical consistency. Explicit and analytical solutions are also given. Compared to TCAD simulations, the model gives excellent results in accumulation regime. Although the accuracy decreases in depletion regime for very high doping and semiconductor thicknesses, it still remains very good and it is shown that this issue can be neglected because it can only be seen on devices with both high doping and semiconductor thicknesses, that are unlikely to be used as a real device, because of their negative threshold voltage. Finally, it is shown that the model reproduces the two observed different conduction modes, related to accumulation and depletion regimes and that the effective gate capacitance and threshold voltage are different in those regimes, which explains the change of slope observed in the Id(Vg) characteristics.

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