Abstract
Synchronous reference frame phase-locked loop (SRF-PLL) is widely used for grid voltage synchronization in single-phase grid-connected power converters. However, in the actual situation, dc offset component may be introduced in the input of the PLL, due to the transient fault of the power grid, sampling and measurement error, or A/D signal processing. A simple yet effective approach with additional all-pass filter based dc rejecter is presented for SRF-PLL, in this paper. Thereby, correct estimation and undesirable periodic ripple free can be achieved in SRF-PLL, when the input signal contains dc offset. The second order generalized integrator based PLL (SOGI-PLL) is first introduced, followed by the analysis on influence of the input dc offsets in SRF-PLL. The structure of enhanced-SOGI (ESOGI) with its analysis of dc offset rejection effects and performance have been then formulated in detail. Finally, experimental results are presented to demonstrate the effectiveness of the proposed ESOGI based PLL.
Highlights
The single-phase grid-tied converter is very important for energy conversion systems, and various applications within the general areas of renewable power generation, such as photovoltaic, fuel cells, residential applications and others [1]–[3]
After the DSP operation, the phase error ε and frequency f of the SOGIPLL, cascade SOGI phase-locked loops (PLLs) and the ESOGI-PLL are obtained by an external DAC
In basis of the inability of conventional SOGI-PLL to eliminate the influence of dc voltage offset, introduced from its input, a new PLL is proposed based on ESOGI, which is reconfigured by SOGI with APF, in this paper
Summary
The single-phase grid-tied converter is very important for energy conversion systems, and various applications within the general areas of renewable power generation, such as photovoltaic, fuel cells, residential applications and others [1]–[3]. Owing to its simple structure and robustness, the synchronous reference frame phase-locked loop (SRF-PLL) is the most popular and widely used technique for the extraction of grid voltage phase, frequency, and amplitude in singlephase grid-tied systems [5]. The dc offset in the PLLs input, introduces the fundamental frequency oscillations in the estimated phase and frequency [10], and may result in the dc injection by the grid-tied converters. B. Liu et al.: Simple Approach to Reject DC Offset for Single-Phase Synchronous Reference Frame PLL in Grid-Tied Converters. Thereby, to preserve the SOGI-PLL simplicity, less computational load, and fast dynamic response, a simple approach to reject dc offset for single-phase SRFPLL using APF is proposed, in this paper. It can be observed that if the actual frequency of ug(s) is equal to the resonant frequency, uα(s)/ug(s) has a unity gain with zero phase shifting. uβ (s)/ug(s) can well extract the fundamental signals from harmonics and noise, but it does not have the ability to restrain dc offset
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
