Abstract

In this paper, an original and simple concept for setting up multi-V T for fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs is presented. Low, standard and high threshold voltage (V T ) devices are achieved without degrading the good channel electrostatic control and the low V T dispersion of the FDSOI technology. The concept is based on the use of a thin buried oxide (BOx) combined with the integration of a doped and biased back plane (BP). This was evaluated by TCAD simulations and benchmarked to the LSTP (Low STandby Power) BULK technology in 45nm technology node. The electrical results highlight the efficiency of the proposed concept. The LVT, SVT and HVT devices show similar results than in the LSTP BULK technology (I ON-LVT =1.35×I ON-HVT ) with I ON /I OFF current ratios higher than 6 decades. Moreover, the concept has been applied to a 6T SRAM cell declined in dual versions: HVT and LVT highlighting excellent cell current ratios (47%).

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