Abstract
A packaging strategy utilizes high-dielectric ultra thin film between power and ground planes is presented. High-dielectric ultra thin film between power and ground planes is used not as an embedded capacitor but a low impedance power distribution route directly connected to the chip. The package has a ground plane in the uppermost layer and power plane in the next metal layer in order to eliminate inductance of vias, and low ESL capacitors are mounted on the surface. Test four-layer organic interposers of 15 mm square were fabricated for a feasibility study of this packaging strategy. As a result it is demonstrated that this structure greatly reduces PDN impedance in higher frequencies and the effectiveness using high-speed CMOS differential drivers.
Published Version
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