Abstract
This paper demonstrates a two-stage 1.95-GHz WCDMA handset RFIC power amplifier (PA) implemented in a 0.25-/spl mu/m SiGe BiCMOS process. With an integrated dual dynamic bias control of the collector current and collector voltage, the average power efficiency of the two-stage PA is improved from 1.9% to 5.0%. The measured power gain is 18.5 dB. The gain variation with dynamic biasing is less than 1.8 dB. An off-chip memoryless digital predistortion linearizer is also adopted, satisfying the 3GPP wideband code division multiple access (WCDMA) linearity specification by a 10 dB improvement of adjacent channel power ratio (ACPR) at +26 dBm average channel output power.
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