A semi-synchronous SAR ADC with variable DAC settling time using a DLL

Abstract

A successive-approximation-register (SAR) analog-to-digital converter (ADC) topology is presented, which optimizes the time distribution during the conversion. It is based on the semi-synchronous timing and uses a delay-looked loop (DLL) for clock generation. The absence of timing determined by analog delays allows an increase of the conversion speed compared to an asynchronous ADC using the same digital-to-analog converter (DAC), comparator and SAR logic. The results of circuit simulations on transistor level confirm the proper operation of the proposed approach.