Abstract
The design of a 6-bit, 100 MHz successive approximation register (SAR) analog to digital converter (ADC) is presented in this paper. The implemented SAR ADC is realized by using SAR logic, a 6-bit DAC, a sample and hold circuit and a comparator circuit. The fully realized system is measured under different input frequencies with a sampling rate of 100 MHz and it consumes 36.7 µW from a 1.8 V power supply. The ADC implemented in 130 nm CMOS technology exhibits signal-to-noise plus distortion ration SNDR of 64.2 dB and occupies a die area of 0.14 mm2.
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