A segmental bus-invert coding method for instruction memory data bus power efficiency

Abstract

This paper presents a bus coding methodology for instruction memory data-bus switching reduction. Compared to the existing state of the art multi-way partial bus-invert coding (MPBI) which relies on data bit-correlation, our approach is very effective in reducing switching activity for bus data, since little correlation can be observed on instruction data buses. Our experiments demonstrate the proposed encoding can reduce up to 42% of switching activity, with an average of 30% reduction, while MPBI achieves just 17.6% reduction in switching activity.