A scheduling scheme with Dynamic Frequency Clocking and multiple voltages for low power designs

Abstract

In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.