A scalable superconducting nanowire memory cell and preliminary array test

Abstract

There has been a demand for a scalable superconducting memory technology for cryogenic computing for some time. This demand has proven difficult to satisfy due to the simultaneous need for high speed operation, low power consumption, and high density, all while maintaining cryogenic and SFQ compatibility. In an effort to satisfy this demand, we have developed a simple memory cell based on our prior work with nanowire-based memories. Due to the memory cell’s reliance on kinetic inductance, the cell can be scaled to almost any size. The cell has been designed specifically such that it can easily form into an array simply by arranging in a 2D pattern. This design eliminated the need for external addressing circuitry. This new cell, when operated in isolation and without the heater, performs very well with predicted bit error rates around 10−17. However, preliminary array tests show that while the memory operates, the predicted error rates rise to 1.5 × 10−3. We believe that this issue is predominantly due to the hTron-channel kinetic inductance dramatically changing upon the application of the row-select heaters. This issue might be addressed by designing the cell to compensate for the change in kinetic inductance when the heater is activated. If this remedy proves to be effective, then this memory would enable the development of compact and scalable memory arrays.