Abstract
An improved scalable single-photon avalanche diode (SPAD) structure with a virtual epitaxial guard ring is presented based on a Bipolar-CMOS-DMOS (BCD) technology. A deep junction between the P-well and the medium-voltage N-well (MVNW) is devised as the avalanche region for the improvement of photon detection efficiency (PDE) and spectral response. Moreover, an N+ buried layer is adopted to enable substrate isolation for the reduction of electrical crosstalk and the facilitation of pixel integration. In particular, a lower doped p-type epitaxial layer is used as a virtual guard ring, which can effectively suppress the dark count rate (DCR) induced by STI-interface traps. The modeling and simulation results indicate that, compared to the P+/P-well/Deep N-well (PWDN) SPAD, the proposed device structure achieves a higher PDE in a wider spectral range, meanwhile, the DCR is also greatly reduced.
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