A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs

Abstract

In this paper, an automatic test pattern generator (ATPG)-based scan-path test point insertion technique, which can achieve high delay fault coverage for scan designs, is proposed. In the proposed technique, the shift dependency between adjacent scan flip-flops, which causes some delay faults to be untestable in the standard scan environment, is broken by inserting test points, which can be combinational gates as well as flip-flops. Instead of topology-based approaches used in prior publications, the proposed technique uses a special ATPG to identify pairs of adjacent scan flip-flops between which test points are inserted to improve fault coverage. Since the proposed technique inserts test points only where they are necessary, it can drastically reduce hardware overhead compared to circuit topology-based techniques. One hundred percent transition delay coverage was attained for all ISCAS 89 benchmark circuits except one. This is achieved with very small numbers of test points. On average, about 40% reduction in scan chain length against a prior approach was achieved by the proposed method for benchmark circuits with default scan chain order.