A Scalable FPGA Architecture for Flexible, Large-Scale, Real-Time RF Channel Emulation

Abstract

Radio Frequency (RF) wireless channel emulators are widely used to test radio networks. They provide a repeatable way to emulate an over-the-air channel in the laboratory. As the size and bandwidth of a radio network grows, it becomes increasingly challenging to implement emulators due to the computation and bandwidth complexity. This paper presents an architecture and work-flow to design and implement high-bandwidth, real-time channel emulators using Software-Defined Radios (SDR), and openly available Field Programmable Gate Array (FPGA) and software libraries. The paper details the steps taken to construct the “Colosseum” testbed, the world's largest channel emulator, built using this architecture. Colosseum is used as a case study to demonstrate the flexibility of this architecture that allows designers to build custom channel emulators based on their specific RF bandwidth, antenna count, channel fidelity and hardware reuuirements.