A re-usable verification framework of Open Core Protocol (OCP)

Abstract

Open Core Protocol (OCP) establishes itself as the only non-proprietary, openly licensed, core-centric protocol that is used to support “plug-and-play” SOC (System-On-Chip) design practices. Designer can reuse OCP-compliance IP cores based on system integration and verification approach in multiple designs without reworking, reducing the development time and cutting down overall design costs. This paper addresses the development of a reusable verification framework of OCP. Assertion-based verification was chosen in order to enforce the flow. An OCP System Verilog monitor which was developed in house is used to verify the OCP SystemC TL1 (Cycle-accurate Level) design. The monitor can also be reused for OCP designs described at different abstraction level and thus dramatically reduce the time needed for OCP functional verification. With proper configuration of this monitor along with our System Verilog Assertion suite, we have found a potential bug in the OCP TL1 implementation which awaits confirmation of the OCP-IP group.