A resource-saving dual channel time-to-digital converter with shared tapped delay line in FPGAs

Abstract

A resource-saving dual channel time-to-digital converter (TDC) in field programmable gate array (FPGA) is presented in this paper. The presented TDC is formed by cascading a channel waveform generator (CWG) and a tapped delay line. Specifically, the CWG can generate six types of waveforms with different transition edges to propagate on tapped delay line according to the different assertion times of two hit signals. Besides, a pipelined encoding module is designed to detect the positions of multiple transition edges on tapped delay line precisely so that the six types of waveforms can be identified and the two hit signals can be distinguished and measured. Since the measurements of two hit signals share one tapped delay line, the TDC based on CWG (CWG-TDC) is a resource-saving dual channel TDC. To evaluate the performance of CWG-TDC, time intervals from 10ns to 200ns were measured on a Xilinx's 40nm Virtex-6 development board. In CWG-TDC, channel 1 and channel 2 can achieve LSB of 9ps, the highest RMS precision of 6.2ps. The consistency between experimental results and theoretical analysis shows that the presented CWG-TDC can not only achieve high RMS precision but also achieve resource-saving.