A Repair-for-Diagnosis Methodology for Logic Circuits

Abstract

Fault diagnosis plays a major role in IC yield enhancement as it can help identify yield limiting defects in fabricated devices. The information on such defects is used to guide modifications to design and/or fabrication processes to improve yield. These steps may be iterated until acceptable yield levels are achieved. Due to circuit structure and limitations of the tests and/or diagnosis procedures used, after the application of tests and logic diagnosis, many detectable faults remain undistinguished from each other and are reported out as suspected defects, thus limiting diagnostic resolution and affecting ability to pinpoint yield limiting defects. This paper proposes a repair-for-diagnosis method to distinguish undistinguished fault pairs in logic circuits to improve diagnostic resolution and hence facilitate the determination of yield limiting defects. Even functionally equivalent faults which cannot be distinguished by any tests can be distinguished using the proposed method. The method proposed augments a circuit under consideration by adding redundant logic that allows repair of a fault to distinguish it from other faults in a group of undistinguished faults. Procedures to efficiently use the proposed repair strategy are given. Once the yield limiting defects are identified and corrective actions in the design and manufacturing process are done, the additional logic of repair-for-diagnosis can be deleted from the final design for volume production with desired yields. Experimental results on ISCAS-89 and IWLS05 benchmark circuits demonstrate the efficacy of the proposed method to improve diagnostic resolution.