A regular architecture for a low-quantum-cost n-bit multiplier

Abstract

Multiplication is a fundamental operation in quantum circuits that plays a crucial role in many quantum algorithms and applications. This manuscript proposes a new architecture for an n-bit unsigned multiplier based on a regular structure consisting of Feynman gates for duplication, BME gates for partial multiplication, and HNG and Peres gates for the final adder part. The proposed multiplication technique is compared with previous research circuits, and the results demonstrate that it has a better quantum cost. The proposed architecture has the potential to significantly improve the efficiency and performance of quantum multipliers. On average, the proposed design gains an improvement of 15.7 % in terms of quantum cost over the best-known existing approach. The proposed architecture has several advantages over existing approaches, such as regularity, simplicity, and lower quantum cost.