Abstract
A construction method is described for a fast parallel adder by using a redundant binary code (RBC). The RBC used has a fixed radix 2 and a digit set {−1,0,1}. The fast parallel adder is composed of ternary-valued CMOS gate networks, which are used in the symmetric ternary logic system, and its construction can be optimized with them.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.