A reconfigurable Network-on-Chip architecture to improve overall performance and throughput

Abstract

Nowadays reconfigurable Network-on-Chip (NoC) is common high performance on-chip communication architecture for multi-core System-on-Chips (SoCs). This paper improved overall performance of reconfigurable NoC and throughput by using some extra switches and multiplexers. In the proposed architecture, some routers are replaced with 5-port switches. Simple 5-port switches are used for making a shorter path between communicating nodes. In another words, the proposed method can set up direct links between processing elements (PEs) by bypassing the intermediate routers. Static Random Access Memory (SRAM) cells are used to program switches and multiplexers in order to connect (or disconnect) the partial paths which leads to configuration capability in NoC. In order to evaluate the proposed architecture we compared it with the Reconfigurable Network-on-Chip (RNoC). Applying this technique would decrease the average packet delay about 40%, power consumption about 8% and there would enhance about 15% in the throughput so the overall performance would improve. Because of adding extra switches and multiplexers in each node, the architecture has about 24% area overhead.