A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver

Abstract

A scalable 4-element V-band digital beamforming phased-array receiver (RX) implemented in TSMC 28-nm CMOS integrates both an analog front-end and beamforming functions in the digital back-end (DBE). Each element includes a mixer-first front-end (MFFE), reconfigurable-resolution, oversampled in-phase and quadrature analog-to-digital converters (ADCs), adjustable finite impulse response (FIR) filters and beamforming weights applied at the DBE. The DBE can store pre- and post-beamforming data in a 0.5 Mb SRAM. The MFFE has an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{S}_{11}$</tex> lower than -10 dB across an 8-GHz bandwidth centered around 52.5 GHz, a maximum gain of 27.1 dB and a minimum noise figure of 7.8 dB. The ADC has a maximum SNDR of 21 dB over a 100-MHz bandwidth when configured as a third-order continuous-time delta-sigma modulator. The chip was configured for experiments with low resolution (1-bit) ADCs which use a digitally-controlled dithering method to enhance the array gain. Although the RX only has 4 elements, the intent is to study the ability to recover information using low-resolution ADCs in a massively-arrayed front-end (FE) [1], [2]. Beamsteering at 0° and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$45^{\mathrm{o}}$</tex> is demonstrated, and a maximum QPSK data rate of 400 MS/s with a minimum error vector magnitude (EVM) of -16.2 dB is achieved. The power and area consumption for one element including the FE, ADCs and custom digital interface is 96 mW and 0.18 mm2, respectively. The area for the entire system is 3.3 mm2.