Abstract
FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs) applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures cannot accommodate the high levels of interneuron connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing scalable SNNs on reconfigurable FPGAs. The paper proposes a novel field programmable neural network architecture (EMBRACE), incorporating low‐power analogue spiking neurons, interconnected using a Network‐on‐Chip architecture. Results on the evaluation of the EMBRACE architecture using the XOR benchmark problem are presented, and the performance of the architecture is discussed. The paper also discusses the adaptability of the EMBRACE architecture in supporting fault tolerant computing.
Highlights
Biological research has accumulated an enormous amount of detailed knowledge about the structure and function of the brain
The basic processing units in the human brain are neurons that are interconnected in a complex pattern [1]
The paper illustrates how the EMBRACE architecture supports the routing, biological computation, and configuration of Spiking Neural Networks (SNNs) topologies on hardware to offer scalable SNNs with a synaptic density significantly in excess of what is currently achievable in hardware [7,8,9, 13]
Summary
Biological research has accumulated an enormous amount of detailed knowledge about the structure and function of the brain. Current FPGA routing structures cannot accommodate the high levels of neuron interconnectivity inherent in complex SNNs [3]. This paper presents the EMulating Biologically-inspiRed ArChitectures in hardwarE (EMBRACE) hardware platform for the realisation of SNNs. EMBRACE uses an NoC-based neural tile architecture and programmable neuron cell which address the interconnect and biocomputational resources challenges. The paper illustrates how the EMBRACE architecture supports the routing, biological computation, and configuration of SNN topologies on hardware to offer scalable SNNs with a synaptic density significantly in excess of what is currently achievable in hardware [7,8,9, 13]. The paper discusses the potential opportunities EMBRACE offers in providing a new hardware information processing paradigm which has the inherent ability to accommodate faults via its neural-based structures.
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