A reconfigurable 8-to-12-b 10-MS/s energy-efficient two-step ADC

Abstract

This paper proposes a reconfigurable and energy-efficient 8-to-12-bit 10 MS/s analog-to-digital-converter (ADC), which adopts the SAR-TDC architecture to enhance the power efficiency of the ADC by realizing the fine quantization of the input signals in the time domain. The proposed resolution reconfigurable technique is based on the variability of the VTC gain, setting three modes to cope with different application scenarios. A VTC based on the bidirectional bootstrap switch is adopted to reduce the leakage current and avoid the comparison errors. The PVT robustness is realized by using the PVT inner tracking technique. The chip is designed under a 180-nm CMOS, with the core area being 0.183 mm2. Under a 1-V supply and the Nyquist rate input, the post-simulation results show that the spurious free dynamic range (SFDR) of the three modes is 86.9/70.3/64.8 dB, the effective number of bits (ENOB) is 11.22/9.24/7.78 bit, the power consumption is 202/147/96 μW, and the figure of merit (FoM) is 8.5/24.3/43.7 fJ/conv.-step respectively.