A real-time lane departure warning system based on FPGA

Abstract

This paper presents a vision based Lane Departure Warning System (LDWS) and its implementation on a Field Programmable Gate Array (FPGA) device. It is used as a Driver Assistance (DA) system that supports drivers and helps avoiding accidents. The FPGA technology has the advantages of high-performances for digital image processing and low cost, both of which are the requirements of the DA systems. The main contributions of this work are threefold: 1) a hardware architecture, which combines Single Instruction Multiple Data (SIMD) structure and Single Instruction Single Data (SISD) structure based on FPGA, is implemented. This architecture is in possession of both efficiency and flexibility. Therefore, it can be employed to handle many vision processing tasks in real time; 2) an improved parallel Hough Transform (HT) is introduced. Compared with traditional HT, we move the origin to the estimated vanishing point, so as to reduce the storage requirements and improve the detection robustness; and 3) a simple and efficient warning strategy is presented which can be implemented on FPGA easily. Experiments illustrate the high performance of the introduced system in various common roadway scenes.