Abstract
In this paper, an architecture for real-time digital HDTV video decoding is presented. Our architecture is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. The decoding datapath is synchronized at the block (8 × 8 pixels) level. Unlike other decoding approaches such as the slice bar decoding method and the cross-divide method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. In comparison to data-flow approaches, our method eliminates the complexity associated with tagged data operations. Our anchor picture storage is organized to minimize page-breaks during memory accesses. Simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1,920 × 1,080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbps.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
