A ratio-independent and gain-insensitive algorithmic analog-to-digital converter

Abstract

The design of a new configuration of capacitor-ratio-independent and gain-insensitive algorithmic analog-to-digital converter (ADC) is described. Through the use of switched-capacitor techniques, the proposed new ADC is insensitive to the capacitor-ratio accuracy as well as to the finite gain and offset voltage of the operational amplifiers. The switching error becomes the only major error source. Both SWITCAP and HSPICE (simulation program with IC emphasis) simulations are performed to verify the performance of the new ADC. It is shown that a 14-b resolution at the sampling frequency of 10 kHz can be achieved when the capacitor ratios have a variation of 10% and the finite gain of the operational amplifiers is only 66 dB. The ADC can be realized by simple analog elements in a small chip area. >