A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs

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The SRAM-based FPGA is extremely susceptible to Single Event Upsets (SEUs) on configuration memory which can lead to soft error and malfunction of the circuit. Facing the ever-growing number of configuration bits in modern FPGAs, conventional traversal scrubbing is getting harder to find errors in time, resulting in longer Mean Time to Detect (MTTD) before the error can be corrected by an effective scrubbing. This paper proposes a rapid scrubbing technique that enables an effective scrubbing as early as possible on a SEU occurrence. It applies position-aware Duplication with Compare (DWC) on the critical circuit that reduces the redundancy cost, and links the application circuit with configuration frames that enables the error locating in a greatly reduced number of configuration frames. Our fault injection-based evaluation on a Xilinx Kintex-7 FPGA shows that it can deliver an average of 45% MTTD and 16% Mean Time to Failure (MTTF) improvement with little cost when compared with the conventional traversal scrubbing provided by the Xilinx Soft Error Mitigation (SEM) module.