Abstract

This paper presents the FPGA (Field Programmable Gate Array) implementation and the coupling analysis of a metastability-based random number generator (RNG). The metastability is acquired through exploiting transient effect ring oscillators (TEROs) and the random bit generation is accomplished through irregular sampling of regular waveform method. As the proposed RNG is made up of only digital logic gates, it is prototyped on a Xilinx ZedBoard Zynq-7000 evaluation platform. It is demonstrated that the RNG output bitstream satisfies NIST 800-22 statistical tests of randomness without any need for post-processing and the proposed RNG can provide high data throughput. Furthermore, the proposed RNG uses less number of components compared to previously reported TERO based RNGs, thus enabling lower power consumption and smaller footprint. Additionally, the proposed RNG is subjected to correlation based cryptanalysis study. In classical ring oscillator (RO) based RNGs, the ring oscillators are required to be placed at a distance from each other to avoid locking phenomenon that may occur due to coupling between adjacent ROs. This study demonstrates that unlike classical RO based RNGs, the proposed RNG is insensitive to locking phenomenon and TERO structures are not required to be placed way from each other. Therefore, the proposed method lead to a more compact RNG design compared to classical RO based RNGs.

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