Abstract
This paper describes the latest, full-functionality revision of the high-speed data link board developed for the Phase-2 upgrade of ATLAS hadronic Tile Calorimeter. The link board design is highly redundant, with digital functionality implemented in two Xilinx Kintex-7 FPGAs, and two Molex QSFP+ electro-optic modules with uplinks run at 10 Gbps. The FPGAs are remotely configured through two radiation-hard CERN GBTx deserialisers (GBTx), which also provide the LHC-synchronous system clock. The redundant design eliminates virtually all single-point error modes, and a combination of triple-mode redundancy (TMR), internal and external scrubbing will provide adequate protection against radiation-induced errors. The small portion of the FPGA design that cannot be protected by TMR will be the dominant source of radiation-induced errors, even if that area is small.
Highlights
The Phase-II upgrade of ATLAS [2] is currently expected to take place from 2023 to 2025
Given that many of the systems were produced more than five years before startup, many of the system components in TileCal will be reaching their end of life
Each Front-End Boards (FEB) type is supported by a matching Main Board (MB) [3], which merges the data from all FEBs in the mini-drawer and adds additional services not included in the FEB
Summary
The Phase-II upgrade of ATLAS [2] is currently expected to take place from 2023 to 2025. Given that many of the systems were produced more than five years before startup, many of the system components in TileCal will be reaching their end of life Another motivation for upgrading the TileCal electronics is that the increased luminosity of the upgraded LHC will mean a proportional increase in minimum-bias collisions per bunch crossing. These higher backgrounds will make it increasingly difficult for the existing trigger system to effectively reduce the readout rate to manageable levels while preserving interesting physics. We have decided to partition the electronics and drawer mechanics into smaller, independent units called “mini-drawers”, which are one quarter of the size of the current full drawers. Modern FPGAs have much smaller feature sizes, and are much less vulnerable in this respect
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