A Quantum-Well Charge-Trap Synaptic Transistor With Highly Linear Weight Tunability

Eunseon Yu,Kaushik Roy,Byung-Gook Park,Seongjae Cho

doi:10.1109/jeds.2020.3011409

Abstract

In this work, a novel synaptic transistor has been proposed and analyzed through technology computer-aided design (TCAD) simulation. The proposed device has merits of full-Si processing compatibility, short- and long-term plasticity, high energy efficiency, and linear and symmetric conductance adjustability. The proposed device consists of a quantum-well structure and a charge-trap unit for realizing both short- and long-term memories, respectively. The quantum-well charge-trap synaptic transistor (QW CTS) employs two independent gates to separate inference and weight adjustment operation. An optimally designed and validated QW CTS has demonstrated a highly linear and symmetric weight tunability, with an ultra-low energy consumption of ~1.5 fJ per synaptic event. The QW CTS can be a core element in the hardware-driven Si neuromorphic system.

Highlights

As the demands on big data explosively increase, a serious bottleneck has been revealed in the conventional vonNeumann computing architectures which are fundamentally operated with the physical discrimination between processing and memory units
Hardware-driven neuromorphic systems, in which electronics analogous to the biological nervous system is realized, are gaining a great deal of interest owing to their high scalability in system volume with the help of convergence between logic and memory units
As the number of holes collected in the SiGe QW after band-to-band tunneling (BTBT), the gradual increase in the number of holes occupying the higher energy states makes the holes more likely tunnel into the nitride charge-trap layer by F-N tunneling even at a low voltage on the gate 2, which corresponds to long-term plasticity (LTP) (Fig. 2)

Summary

INTRODUCTION

As the demands on big data explosively increase, a serious bottleneck has been revealed in the conventional vonNeumann computing architectures which are fundamentally operated with the physical discrimination between processing and memory units. As the number of holes collected in the SiGe QW after BTBT, the gradual increase in the number of holes occupying the higher energy states makes the holes more likely tunnel into the nitride charge-trap layer by F-N tunneling even at a low voltage on the gate 2, which corresponds to LTP (Fig. 2). At a high doping concentration of 1019 cm−3, there was a large increase in Vth due to higher energy barrier seen from the valence electrons, which required higher operation voltage, which made the synaptic device not suitable to ultralow-power neural networks. Another critical variable related with the material parameter is Ge content x in the Si1−xGex QW. The nitride layer needs to include deeper traps

WEIGHT INFERENCE AND ENERGY EVALUATION

CONCLUSION