A Quad-Channel 11-bit 1-GS/s 40-mW Collaborative ADC Enabling Digital Beamforming for 5G Wireless

Abstract

A $4 \times 11$ bit 1-GS/s 40-mW collaborative analog-to-digital converter (ADC) is presented in a 65-nm CMOS for a four-channel multiple-input and multiple-output (MIMO) receiver. This work extends the maximal-ratio-combining (MRC) approach to define the ADC resolution in a multichannel environment to maximize the signal-to-noise ratio (SNR) in a power-constrained application. The ADC takes the advantage of the channel diversity by distributing the resolution according to the channel SNR. In addition, it utilizes the correlated information between channels to perform energy-efficient digitization of received signals. The collaborative ADC is designed with eight successive-approximation-register (SAR) ADC units each having a 6-bit of resolution and a 2-bit flash to monitor SNR. With the help of a coarse 2-bit flash, the ADC can detect change in channel SNR and accordingly reconfigure the four ADCs with a variable resolution from 6 to 11 bits with less than 1-ns mode switching time. This collaborative ADC performance is compared with four channel ADCs with uniform 11 and 9 bits of resolution. It reduces area and power by half and 41%, respectively, with only 10% degradation of overall signal-to-noise and distortion ratio (SNDR).