Abstract
AbstractThis paper presents a time division switching network in which only functionally expanded multiplexing switches are connected in cascades. It has been designated Variable Multi‐demultiplexing Time Division Switching Network (VTDS). Input multiplicity is commonly one in the conventional multiplexing switch (switching circuit element); however, the one proposed herein accommodates lines whose multiplicity is more than one. All VTDS holding memories, which store the correspondence between input timeslots and output timeslots, can be realized with the same economical low‐speed memories. Moreover, the switching network structure is optimized assuming that gate cost is proportional to gate speed. the optimum VTDS switch size gradually decreases towards the center stage. an outstanding VTDS feature is that multiplexing switching gate speed can be utilized most effectively because VTDS needs no time memory and speech path network construction is freed from random access memory speed limit. Other VTDS features: (1) input multiplicity is one; (2) channel graph is serial‐parallel type; and (3) it eliminates highway (space) switches.
Published Version
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