A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End

Abstract

Sub-sampling down-conversion mixers have not been considered as a mixer-first RF front-ends due to their disadvantages of high noise figure and lack of impedance matching at the RF port, even though they offer the advantages of less complex clocking circuits and low-power consumption. In this work, a process scalable architecture for low noise figure impedance matched sub-sampling mixer-first RF front-end is proposed addressing the issues of noise folding and impedance matching with process scalable circuit components like switches, capacitors and inverters. A scheme to reject the selected IF odd-harmonics of fs/4 by multi-path sampling is proposed, alleviating the effect of noise folding and leading to low noise figure sub-sampling mixer-first RF front-end. The combination of the complex impedance band-pass filter along with the IF-LNA provide the tuned impedance matching. In addition, analysis on sub-sampling frequency plan, amount of harmonic rejection and its effect on noise figure, transparency of the impedance at the RF port and its tunability with respect to the input impedance of IF-LNA is presented. To validate the analysis and modeling, as well as to explain the architecture, an example low-power narrow-band IoT(NB-IoT) standard RF front-end is realized in 1.2 V, 65 nm CMOS and it is observed that the performance predicted by analytical equations is in agreement with Spectre RF simulations.