A Process for 0.5 Micron CMOS Gate Definition

Abstract

ABSTRACTA RIE process has been developed for the etching of 0.5 μm CMOS Polysilicon gates defined using both E-Beam direct writing and sub-micron optical lithography. Profile control and selectivity were enhanced by using a two-step pattern transfer process wherein the Photoresist mask was used to define a thin Silicon Nitride layer which was subsequently used to define the underlying Polysilicon gate electrode. High etch selectivity to both the Silicon Nitride mask and the thin gate oxide was achieved using a Cl2 plasma chemistry after a BCl3 initiation step. The effect of BCl3 initiation on the poly profile and the effect of loading on profile and selectivity will be presented.