A probabilistic fault model for 'analog' faults in digital CMOS circuits

Abstract

A probabilistic approach to the detection of analog faults (i.e. transistors stuck-on and bridgings) in CMOS circuits that depends on the conductances of faulty and fault-free networks is presented. It is shown that unrealistic fault coverages can be obtained by simply assigning constant values to the conductances of transistors and bridgings and by comparing the resultant conductances of faulty and fault-free conflicting networks. To solve this problem, all conductances are considered as random variables with normal distribution. Conductance distributions of complex conflicting networks can be easily evaluated, and the detection probability of each fault is determined. The expected coverage of analog faults is known at the end of a fault simulation. This result is shown to be more realistic than those obtained in a deterministic way. Fault coverages of analog faults obtained by means of a gate-level fault simulator are discussed for a complex FCMOS benchmark. >