A Predictive 3-D Source/Drain Resistance Compact Model and the Impact on 7 nm and Scaled FinFETs

Abstract

Due to the increasing importance and complexity of source/drain parasitic resistance (Rsd) in nanoscale CMOS technology and circuit design, a predictive 3-D structure-aware Rsd compact model is developed and comprehensively validated in respect of 7-nm bulk FinFET TCAD platform. Our TCAD model was calibrated against GlobalFoundries/Samsung 7-nm FinFET technology experimental data and further validated by 2-D Poisson–Schrodinger simulation. Verilog-A coded SPICE Rsd compact model, coupled with proper transport models, indicates that the degradation of saturation current as well as the proportion of Rsd to total device resistance continues to increase from 45% to 49%, and 52% with the scaling of the FinFET from 7 to 5, and 3-nm FinFETs, with errors of less than 4%. TCAD and compact model simulation results both show that the extension and epitaxial contact regions become dominant while metal contact resistivity can be reduced below 6– ${8} \times {10}^{-{9}} \,\, \Omega \cdot \text {cm}^{{2}}$ .