Abstract
DG-MOSFETs are the most widely explored device architectures for nano-scale CMOS circuit design in sub-50 nm due to the improved subthreshold slope and the reduced leakage power compared to bulk MOSFETs. In thin-film (tsi by tsi- induced quantum confinement along with the confinement caused by a very high electric field at the interface. Therefore, quantum confinement effects on the device characteristics are also quite important and it needs to be incorporated along with short channel effects for nano-scale circuit design. In this paper, we analyzed a DG-MOSFET structure at the 20 nm technology node incorporating quantum confinement effects and various short channel effects. The effect of physical parameter variations on performance characteristics of the device such as threshold voltage, subthreshold slope, ION - IOFF ratio, DIBL, etc. has been investigated and plotted through extensive TCAD simulations. The physical parameters considered in this paper are operating temperature (Top), channel doping concentration (Nc), gate oxide thickness (tox) and Silicon film thickness (tsi). It was observed that quantum confinement of charge carriers significantly affected the performance characteristics (mostly the subthreshold characteristics) of the device and therefore, it cannot be ignored in the subthreshold region-based circuit design like in many previous research works. The ATLASTM device simulator has been used in this paper to perform simulation and parameter extraction. The TCAD analysis presented in the manuscript can be incorporated for device modeling and device matching. It can be used to illustrate exact device behavior and for proper device control.
Highlights
The conventional bulk MOSFETs pose scaling limitations beyond 50 nm technology node because of increased Short Channel Effects (SCEs), increased gateoxide tunneling currents [1] [2] and remarkable mobility degradation [3] [4] [5]
The results are demonstrated by extensive 2-D TCAD simulation and confirmed analytically at various technology nodes to validate the robustness of the model
The proffered physical models and the proposed device may be utilized in the progression of reliable and trustworthy TCAD simulation tools for nanodevices
Summary
The conventional bulk MOSFETs pose scaling limitations beyond 50 nm technology node because of increased Short Channel Effects (SCEs), increased gateoxide tunneling currents [1] [2] and remarkable mobility degradation [3] [4] [5]. These scaling limits can be overcome by the use of DG-MOSFET structures. It can be used to illustrate exact device behavior and for proper device control It can be used for checking technological parameter fluctuations, reliability evaluation factors, etc
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