A Power-Efficient FPGA-Based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution

Abstract

System-level mixed-criticality design towards low product cost and high resource efficiency. This paper studies the integration technology of mixed-criticality avionics traffics for Avionics Full-Duplex Switched Ethernet (AFDX) network, which can transmit both critical traffics and non-critical traffics. In the architecture, critical traffics use by Bandwidth Allocation Gap (BAG) based scheduler and non-critical traffics are scheduled by Round Robin manner. In order to estimate delay bound meeting requirements of applications, End-to-End delay for both critical traffics and non-critical traffics are analyzed exerting the approach of Network Calculus. Finally, a True Time based simulation of AFDX networks is conducted to show the effectiveness of proposed approach.