Manufacturing Shop-Floor Supercomputer for Distributed Simulation and Control

Abstract

Computing for manufacturing systems is important for scheduling and control of manufacturing processes and systems that ensure production throughput, delivery timeliness and reducing inventory. Optimal decisions in such situations are generally intractable and the solutions are required in real-time (few seconds). This motivates the need for a custom supercomputer. At present computing infrastructure in manufacturing enterprises such as ERP and MRP software essentially provide track operational data but are well integrated with equipment on shop floor. Therefore such software systems do not possess real-time information about health of machine or its capacity. Secondly, it does not support any level of optimal decision-making. Thus there is a need for computing architectures that can be integrated with existing enterprise IT infrastructure and can be distributed throughout the shop-floor by embedding it in the information sources such as machine tools, part pallets, inspection equipment etc allowing unification of system level and equipment level control. Distributed Arrival Time Control (DATC) is a new class of algorithm for real-time decisionmaking and control in manufacturing enterprises. Applications of DATC include production scheduling, maintenance scheduling, transportation routing, inventory control, supply chain management, etc. DATC is a highly distributed feedback control approach that uses feeback from simulations to iteratively refine and improve decisions. There are two fundamental simulation approaches that can be used for providing feedback to DATC: Distributed Event Simulation (DES) and Distributed Time Scaled Simulations (DTS). Both the techniques have their advantages and disadvantages. DES is suitable for sequential computing and does not scale well to parallel architectures. DTS is communication intense and but is ideal for parallel/distributed architectures. The objective of our research is to develop custom reconfigurable computing architectures using field programmable gate arrays (FPGAs) for advantageously using inherent parallelism in DATC/DTS. DATC/DTS has well defined communication protocol that requires communication network such as Ethernet to support message passing. The current work is an implementation of DATC/DTS over a distributed FPGA platform interconnected over a fast Ethernet. This architecture eliminates the communication protocol and operating system overhead that typically limits the scalability of general-purpose computers. In our architecture, FPGA nodes are heavily pipelined and rich in computing resources. Each node consists of a communication block and application blocks. A communication block consists of Layer-2 (OSI), Funnel (Interface) and System Bus Controller (SBC) implementations. Use of layer-2 in the communication stack ensures that frames used for message exchange are Ethernet compatible. This allows network fabric for architecture to support COTS Ethernet switching and thus improve overall bandwidth utilization. Funnel is used to maintain consistent interface protocol between application block and the communication block. Funnel enables Layer-2 of the communication block to be migrated to Gigabit Ethernet and other protocols without crucial change in the application blocks. SBC connects communication block and application blocks with data, address and control buses, enabling several application blocks to be connected in parallel and to ease the interface. Each application block on the FPGA node is designed to hold a single DATC controller. Some of the core logical units used in design of DATC controller of FPGA node include FSM, single precision Floating Point Adder/Multipliers, Bus Interface Logic, Timers, Float to Integer