A Power-Efficient and Fast-Locking Digital Quadrature Clock Generator with Ping-Pong Phase Detection

Abstract

This work presents a low-power and fast-locking digital 1.6GHz quadrature clock generator (QCG), which mainly consists of a novel ping-pong phase detection (PPD) controller with a pair of latch-based phase detectors. The proposed PPD scheme compares generated clock signals from a digitally controlled delay line (DCDL) with an input clock for fast coarse lock, resulting in a short locking time. Post-layout simulations of an implementation in 28nm CMOS technology suggest that the proposed work can lock within 13 cycles and produce 4-phase 1.6GHz quality output clocks, which supports a data rate of 6.4Gbps. It achieves an RMS jitter of 1.65ps and an effective peak-to-peak jitter of 1.12ps, offers power efficiency of 0.25mW/Gbps, and occupies an area of 0.00247mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .