A PLL-based synthesizer for tunable digital clock generation in a continuous-time [formula omitted] A/D converter

Abstract

In this paper, the design and implementation of a tunable clock synthesizer for driving two continuous-time Σ Δ ADCs has been carried out. A PLL-based solution, whose phase noise requirements are obtained from system level simulations, was implemented in a 0.35 μ m CMOS technology. The frequency of the clock ranges from 12 to 256 MHz with a minimum tuning step of 10 kHz . The PLL phase noise is kept below - 80 dBc / Hz at 1 MHz offset for the entire output range, while drawing 2.2–5.6 mA from a 3.3 V supply voltage.