Abstract
A burst image sensor named Hanabi, meaning fireworks in Japanese, includes a branching CCD and multiple CMOS readout circuits. The sensor is backside-illuminated with a light/charge guide pipe to minimize the temporal resolution by suppressing the horizontal motion of signal carriers. On the front side, the pixel has a guide gate at the center, branching to six first-branching gates, each bifurcating to second-branching gates, and finally connected to 12 () floating diffusions. The signals are either read out after an image capture operation to replay 12 to 48 consecutive images, or continuously transferred to a memory chip stacked on the front side of the sensor chip and converted to digital signals. A CCD burst image sensor enables a noiseless signal transfer from a photodiode to the in-situ storage even at very high frame rates. However, the pixel count conflicts with the frame count due to the large pixel size for the relatively large in-pixel CCD memory elements. A CMOS burst image sensor can use small trench-type capacitors for memory elements, instead of CCD channels. However, the transfer noise from a floating diffusion to the memory element increases in proportion to the square root of the frame rate. The Hanabi chip overcomes the compromise between these pros and cons.
Highlights
In 1991, Etoh developed a video camera with a parallel readout high-speed image senor of 4500 fps [1]
The cascade branching begins from a guide gate (GG), hexa-furcating to first-branching gates (FG), each bifurcating to second-branching gates (SG), each connected to a floating diffusion (FD) for storage and readout of signal electrons, and further connected to a reset gate (RS) and a reset drain (RD)
A burst image sensor is a standard technology for ultra-highspeed imaging, using either CCD or CMOS technologies
Summary
In 1991, Etoh developed a video camera with a parallel readout high-speed image senor of 4500 fps [1]. In response to requests from users of this camera for a much higher frame rate, Etoh and Takehara proposed an image sensor concept with in-pixel multiple analogue storage elements, targeting 30 Mfps in 1992 [2]. In 1996, Kosonocky et al achieved 0.5 Mfps with an image sensor with in-pixel series-parallel-series (SPS) CCD storage [3]. He named such an image sensor with in-pixel storage for ultra-highspeed imaging “a burst image sensor”. In 2001, Etoh et al reached 1 Mfps for the first time with an in-situ storage image sensor with a slanted linear CCD for each pixel [4].
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