A pipelined subranging analogue-to-digital video convertor with time-interleaved sampling

Abstract

Video analogie-to-digital convertors are mostly based on the subranging flash and two-step flash architectures owing to their reduced silicon area and power consumption, and also because their operating frequency can be easily extended towards higher frequencies through the adoption of either time-interleaved or pipelined techniques. In this paper an alternative subranging analogue-to-digital convertor architecture is proposed in which the time-interleaved and pipelined techniques are jointly employed in order to achieve further saving of the die area and allow more relaxed speed requirements of the comparators in the flash quantizers. For visiophony applications, with 8-bit resolution and 13·5 MHz conversion frequency, this convertor has been constructed in integrated circuit form using a 1·2 μm CMOS technology, yielding an active area of 2·18 mm 2 and a power consumption of 170 mW.