A pipelined 32 b microprocessor with 13 kB of cache memory: A Berenbaum (AT&T Inf. Syst., Holmdel, NJ, USA), B W Colbry, D R Ditzel, R D Freeman, H R McLellan, M Shoji, K J O'Connor 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA:

doi:10.1016/s0026-2692(88)80165-4

A pipelined 32 b microprocessor with 13 kB of cache memory: A Berenbaum (AT&T Inf. Syst., Holmdel, NJ, USA), B W Colbry, D R Ditzel, R D Freeman, H R McLellan, M Shoji, K J O'Connor 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA:

https://doi.org/10.1016/s0026-2692(88)80165-4

Copy DOI

Journal: Microelectronics Journal

Publication Date: Sep 1, 1988

#International Solid State Circuits Conference #IEEE International Solid State Circuits + Show 8 more

Abstract
Full-Text PDF
Similar Papers

Abstract

A pipelined 32 b microprocessor with 13 kB of cache memory: A Berenbaum (AT&T Inf. Syst., Holmdel, NJ, USA), B W Colbry, D R Ditzel, R D Freeman, H R McLellan, M Shoji, K J O'Connor 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA:

Full Text