A Physics-Based Compact Model for Silicon Cold-Source Transistors

Abstract

Silicon-based cold-source transistors are promising for energy-efficient logic switches and hence for semiconductor technology node scaling due to their subthermal switching capability, good ON-state performance, and compatibility with existing process technology. Owing to the importance of compact models in advancing semiconductor technology, we propose a compact model for silicon-based dual-gate cold-source field-effect transistors (DG-CSFETs). Our core model is charge-based and provides an explicit solution for surface potential, terminal charges, and drain current. The density of the cold carrier in the channel injected from the source is included physically in the developed model. In addition, we include the impacts associated with small device geometry. Furthermore, we verify the developed model against quantum transport simulations. Our model accurately captures the drain-current behavior with different geometric parameter scaling. To the best of our knowledge, this is the first compact model developed for cold-source transistors.