A physical insight into the quasi-saturation effect in VDMOS power transistors

Abstract

The physical mechanisms that cause quasi-saturation phenomena in a commercial 500 V VDMOS device are studied and modelled using a two-dimensional numerical simulator. It is found that there exist two mechanisms that limit the drain current and lead the device into quasi-saturation. These are the formation of a gate independent dipole layer, and the high resistivity of the drift region. A modified VDMOS structure with an ion-implanted region is proposed which increases the drain current carrying capability and reduces the on-resistance by up to 60%.