A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> State-of-the-art phase-domain all-digital phase-locked loops (ADPLLs) require a retimed reference clock to synchronize the digitally controlled oscillator (DCO) output frequency and the reference clock frequency. Therefore, the entire digital logic is operated with a periodically nonuniform clock. Due to on-chip coupling effects, the DCO output frequency is pulled with the edges of the retimed reference clock, producing undesired spurs in the phase noise power spectrum. In this brief, we analyze and classify the spur generation from a signal processing point of view and propose an alternative ADPLL implementation that abandons the retiming mechanism. Thus, the entire ADPLL can be clocked with a uniform reference clock, and consequently, side spurs are avoided. Behavioral simulations verify the spur analysis and emphasize the improved behavior of the proposed synchronous reference architecture. </para>