A Parametric DFT Scheme for STT-MRAMs

Abstract

Process control and yield of spin torque transfer-magnetoresistive random access memory (STT-MRAM) array are of crucial importance in fabrication. While yield depends on the CMOS process variability, quality of the deposited MTJ film, and other process nonidealities, test platform can enable a parametric optimization and verification process using the CMOS-based design-for-testability (DFT) circuits. In this paper, we develop a DFT algorithm and implement a DFT circuit for parametric testing and prequalification of the critical circuits in the CMOS wafer. The DFT circuit successfully replicates the electrical characteristics of MTJ devices and captures their spatial variation across the wafer with an error of less than 4%. We estimate the yield of the read sensing path by implementing the DFT circuit, which can replicate the resistance-area product variation up to 50% from its nominal value. The yield data from the read sensing path at different wafer locations are analyzed, and a usable wafer radius up to 75 mm has been estimated. Our DFT scheme can provide quantitative feedback based on in-die measurement, enabling fabrication process optimization through iterative estimation and verification of the calibrated parameters.