A Parallel Transmission Scheme Based on the Turbo Product Code for Through Silicon via Array in Three-Dimensional Integrated Circuits

Abstract

Through silicon via (TSV) is the key technology for the vertical interconnect in three-dimensional integrated circuits (3-D ICs). With the help of TSVs, higher throughput in signal transmission can be attained. However, the tightly clustered TSVs in the TSV array suffer from crosstalk noise, a situation which results in transmission errors. This study investigates, the channel model of the TSV array, involving main factors affecting transmission performance, such as transmission loss, inter-channel interference, and crosstalk noise with different digital patterns. A parallel transmission scheme based on a turbo product code (TPC) parallel coding is proposed. In this scheme, the binary bits of information are reshaped into two dimensional blocks. Each block is parallel encoded using a TPC into a codeword block for parallel transmission through the TSV array channel. At the receiver, the sending information is reformed by a concurrent hard decision decoding algorithm of a TPC. This parallel transmission scheme achieves low bit-error-rate, high throughput, and a lower system overhead relative to that of its ground TSV shielded counterpart if the type of TPC is carefully selected. The simulation results confirm that this scheme reduces inter-symbol interference, minimizes structural defects in the TSV array, and improves transmission performance in 3-D ICs.